1. Field of the Invention
The present invention relates to a semiconductor device including a pillar MOS transistor and a method of manufacturing the same.
Priority is claimed on Japanese Patent Application No. 2009-257152, filed Nov. 10, 2009, the content of which is incorporated herein by reference.
2. Description of the Related Art
Regarding pillar MOS transistors (vertical MOS transistors), a gate electrode covers a side surface of a pillar, and a diffusion layer, which is a source and/or drain, is formed in a top portion of the pillar. For this reason, it is difficult to connect the gate electrode to a wire in an upper layer. To solve the problem, Japanese Patent Laid-Open Publication No. 2008-288391, No. 2009-10366, and No. 2009-81389 disclose semiconductor devices including not only a transistor pillar including a gate electrode, but also a dummy pillar adjacent to the transistor pillar. A dummy gate electrode, which covers a side surface of the dummy pillar, is formed so as to be connected to the gate electrode of the transistor pillar. The dummy gate electrode is connected to a wire in an upper layer via a gate contact. Thus, a voltage is supplied to the gate electrode of the transistor pillar via the dummy gate electrode.
FIG. 13 is a plan view illustrating an arrangement of a transistor pillar 1 and a dummy pillar 2 of the related art, which is viewed from a direction perpendicular to a main surface of a substrate. Regarding a silicon mono-crystalline substrate used for manufacturing a semiconductor device, a notch portion, which indicates a crystal face orientation, is formed in a (110) plane. A <110> direction is perpendicular to the (110) plane. A general semiconductor circuit is laid out on a substrate surface based on two equivalent orthogonal <110> directions. For this reason, the transistor pillar 1 and the dummy pillar 2 are aligned in the <110> direction, as shown in FIG. 13.
FIGS. 14 to 19 are cross-sectional views indicative of a process flow illustrating a method of manufacturing a pillar MOS transistor of the related art. Firstly, an insulating film 3 is formed on a main surface of a silicon substrate 4. Then, the insulating film 3 is patterned to form insulating films 3A and 3B that are bases for forming the transistor pillar 1 and the dummy pillar 2. Then, the transistor pillar 1 and the dummy pillar 2 are simultaneously formed using the patterned insulating films 3A and 3B as masks, as shown in FIG. 14. The transistor pillar 1 and the dummy pillar 2 are circular in plan view. At this stage, an orientation of the transistor pillar 1 and the dummy pillar 2 is not considered. Consequently, the transistor pillar 1 and the dummy pillar 2 are aligned in the <110> direction, as shown in FIG. 13.
Then, the exposed side surfaces of the transistor pillar 1 and the dummy pillar 2 and the exposed main surface of the silicon substrate 4 are cleansed. Then, a thermal oxide film 6 is formed so as to cover the exposed side surfaces of the transistor pillar 1 and the dummy pillar 2 and the exposed main surface of the silicon substrate 4. Then, a dopant is introduced into near-surface regions of the silicon substrate 4 which are adjacent to bottom portions of the transistor pillar 1 and the dummy pillar 2, so as to form lower diffusion layers 5, as shown in FIG. 15.
Then, portions of the thermal oxide film 6, which cover the side surfaces of the transistor pillar 1 and the dummy pillar 2, are removed using a chemical solution. Then, a gate insulating film 7 is formed by thermal oxidization so as to cover side surfaces of the transistor pillar 1 and the dummy pillar 2, as shown in FIG. 16.
Then, gate electrodes 8A and 8B are formed so as to cover the side surfaces of the transistor pillar 1 and the dummy pillar 2 through the gate insulating films 7, respectively, as shown in FIG. 17. In this case, a thickness of each of the gate electrode 8A and 8B is set to a value that is larger than half of the distance between the transistor pillar 1 and the dummy pillar 2 so that the gate electrodes 8A and 8B contact each other.
Then, an inter-layer insulating film 10 is formed so as to cover the insulating films 3A and 3B covering the upper surfaces of the transistor pillar 1 and the dummy pillar 2. Then, a portion of the inter-layer insulating film 10, which covers an upper surface of the insulating film 3A, is removed. Then, the insulating film 3A on the transistor pillar 1 is removed so as to expose the upper surface of the transistor pillar 1. Thus, a hole is formed in the inter-layer insulating film 10. Then, an insulating film 10A is formed so as to cover a side surface of the hole. Then, an upper diffusion layer 9 is formed in a top portion of the transistor pillar 1, as shown in FIG. 18.
Then, an inter-layer insulating film 10C is formed over the inter-layer insulating film 10A. Then, first to third contact holes are formed so as to partially expose the lower diffusion layer 5, the upper diffusion layer 9, and the gate electrode 8A, respectively. Then, first to third contacts 11 to 13 (the first contact 11 is not shown) filling the first to third contact holes are formed, as shown in FIG. 19. Then, wires (not shown) are formed so as to be connected to the first to third contacts 11 to 13.
As explained above, the above method includes the thermal oxidization process, the etching process, and the cleaning process. A thermal oxidation rate and an etching rate of silicon depend on a crystal face orientation. For example, a thermal oxidation rate and an etching rate of the (110) plane are greater than those of the (100) plane. Since the transistor pillar 1 and the dummy pillar 2 are formed by etching the silicon substrate 4, both a Si (110) plane and a Si (100) plane are included in each of the side surfaces of the transistor pillar 1 and the dummy pillar 2.
For this reason, the thermal oxide film 6 covering the (110) plane of the pillar side surface is thicker than the thermal oxide film 6 covering the (100) plane of the pillar side surface. Since the thermal oxide film 6 is removed by a chemical solution, the <110>-directed pillar diameter becomes smaller than the <100>-directed pillar diameter.
Further, if the thermal oxide film 6 is removed by a chemical solution, a larger area of the (110) plane is subjected to the chemical solution than the (100) plane. Accordingly, the <110>-directed pillar diameter becomes further smaller than the <100>-directed pillar diameter.
In this manner, if the thermal oxidation process, the etching process, and the like are repeated, the (110) plane is removed faster than the (100) plane. The <110>-directed pillar diameter is reduced by approximately 15 nm from the original pillar diameter when the pillar is formed. Additionally, the pillar shape is a circle in plane view before the thermal oxidation process, the etching process, and the like are carried out. After these processes, the pillar shape changes to substantially a rectangle in plan view, as shown in FIG. 20. The (110) plane of the transistor pillar 1 and the (110) plane of the dummy pillar 2 face each other. As explained above, the thermal oxidation rate and the etching rate of the (110) plane is greater than those of the (100) plane. For this reason, a speed at which the distance between the transistor pillar 1 and the dummy pillar 2 (the minimum distance between side surfaces of the pillars 1 and 2) increases is faster when the two (110) planes face each other than when the two (100) planes face each other and when the (100) plane faces the (110) plane. Specifically, the distance between the pillars 1 and 2 increases at double a speed at which the (110) plane is removed in a direction perpendicular to the (110) plane.
For example, when pillars are formed with the feature size of 50 nm (diameter and pitch), the <110>-directed pillar diameter and interval after a pillar MOS transistor is complete are 35 nm and 65 nm, respectively. For this reason, to make the gate electrode 8A of the transistor pillar 1 contact the gate electrode 8B of the dummy pillar 2, a thickness of the gate electrode has to be set to 33 nm or more. In consideration of a variation in pillar diameter and the like, a thickness of the gate electrode 8 has to be set to approximately 45 nm or more.
If the gate electrodes 8A and 8B are thicker, a greater stress acts on silicon portions of the transistor pillar 1 and the dummy pillar 2, thereby causing an increase in a junction leakage current of the upper diffusion layer 9, a variation in threshold voltage, and the like. Particularly when the gate electrodes 8A and 8B are made of a metal, the effects of the increase in a junction leakage current, the variation in threshold voltage, and the like become greater. For this reason, it is necessary to make the gate electrodes 8A and 8B thinner. However, the above pillar MOS transistor of the related art cannot achieve thinner gate electrodes 8A and 8B.